Integrated circuits have utilized bipolar junction transistors for many years, taking advantage of their high gain characteristics to satisfy high performance and high current drive needs. In particular, as is well known in the art, bipolar transistors are especially well-suited for high frequency applications, such as now used in wireless communications.
Silicon-on-insulator (SOI) technology is also well-known in the art as providing important advantages in high-frequency electronic devices. As is fundamental in SOI technology, active devices such as transistors are formed in single-crystal silicon layers formed over an insulator layer, such as a layer of silicon dioxide commonly referred to as buried oxide (BOX). The buried oxide layer isolates the active devices from the underlying substrate, effectively eliminating parasitic nonlinear junction capacitances to the substrate and reducing collector-to-substrate capacitances. To the extent that high frequency performance of bulk transistors was limited by substrate capacitance, SOI technology provides significant improvement.
In addition, SOI devices are robust in high voltage applications. The buried oxide layer effectively eliminates any reasonable possibility of junction breakdown to the substrate.
However it has been observed that those transistor features that facilitate high frequency performance tend to weaken the device from a high bias voltage standpoint, and vice versa. This tradeoff has typically been addressed by separately manufacturing high voltage integrated circuits and high performance integrated circuits, with each integrated circuit having transistors optimized for their particular implementation. This is because the process complexity resulting from integrating both high voltage and high performance devices in the same SOI integrated circuit adds significant cost and exerts manufacturing yield pressure.
A conventional SOI bipolar transistor is designed to be a high performance device. However, a high performance transistor is somewhat limited by its construction, from a standpoint of both breakdown voltage and performance. As is fundamental in the art, the collector emitter breakdown voltage (BVCEO) depends upon the thickness of collector region and upon the doping concentration of the collector region. Lighter doping of the collector region and a thicker collector region would increase this breakdown voltage.
In a real circuit, the emitter and base of a PNP is biased around the highest potential Vcc (relative to grounded substrate) while the collector is switched between Vcc and 0. High B-C bias corresponds to zero potential at collector. At this condition grounded p-substrate does not deplete lateral portion of collector region and, hence, does not help to increase BV.
The emitter and base of an NPN is biased around the lowest potential GND (relative to grounded substrate) while the collector is switched between Vcc and 0. High B-C bias corresponds to VCC potential at collector. At this condition grounded p-substrate depletes lateral portion of collector region and, hence, helps to increase V.
What is needed is a method of increasing PNP BV without decreasing collector doping concentration or increasing collector region thickness of the PNP while including a high voltage NPN on the same circuit/substrate.